OSATE includes a set of built-in examples that could help you to start learning the languages or see what modeling patterns are useful for the analysis plugins. There is a traceability matric between Analysis Plug-In and the examples, showing which example can be used with each analysis plugin.
|Flow Latency||Weight Analysis||A429 consistency||Port Connection Consistency||Bus Load (bound)||Power Requirements||Resources Allocation (bound)||Resources Allocation (not bound)||Connection Binding Consistency||Fault-Tree Analysis||Functional Hazard Assessment||Fault Impact||Common Mode Analysis||Reliability Block Diagram||Bind a Schedule Threads||Schedule a Bound System||Check Priority Inversion|
|multi tier aircraft||yes||yes||yes||yes||yes||yes||yes||yes||yes||no||no||no||no||no||yes||yes||yes|
Good practices for Software Architecture
Several AADL models representing good architecture practices are proposed. In particular, it illustrates good architecture patterns with AADL and shows how to analyze architecture that do not use them or does not use it efficiently. All our patterns are defined on a following page.
Multi Tier Aircraft and Other ALISA Examples
We have several larger scale AADL examples. They have been prepared to be used with the Architecture-Led Incremental System Assurance (ALISA) capability of OSATE, which is part of Release 2.2.1 or later. The Multi Tier Aircraft example demonstrates a wide range of analysis plug-ins, as well as the use of requirement specifications and verification plans to automate the incremental verification of AADL models.
Two of the examples are the basis for a tutorial. One is the SimpleControlSystem with the tutorial found at System Requirements and Verification.
The details of weight analysis can be found at this page.
Hardware Resource Budget Analysis
The details of MIPS, Memory, and Network Bandwidth Resource Budget Analysis can be found at this page.
Electrical Power Analysis
The details of Electrical Power Transmission Analysis can be found at this page.
OSATE supports latency analysis. The capabilities of latency analysis are described on this dedicated page.
Multi-level Fault Tree Analysis
We put together a Multi-level Fault Tree Analysis tutorial that illustrating the use of fault tree analysis during multiple steps of the development. It utilizes a graphical fault tree editor that can also be used as a standalone Eclipse tool SEI Blog Poston EMFTA.
The model is available on Github.
Tutorial on Latency, Safety, and Security (EMSOFT 2016 )
This tutorial exercises an example AADL model with latency, safety and security analysis.
An SEI Blog provides details on the security aspect of the tutorial.
You can get more information on the ESWeek 2016 tutorial on this dedicated page
Code Generation Demonstration for ARINC653
The code generation demonstration for ARINC653 shows how to generate code from AADL while targetting ARINC653 operating systems such as DeOS or VxWorks653. The code focuses on two main models:
- ADIRU: generation of the module configuration (XML file) and partitions code (C code) from the AADL model and integration of user code (C code written manually)
- SCADE integration: generation of the module configuration (XML file) and partitions code (C code) from the AADL and integration of user code from SCADE.
Details and information can be found in a dedicated page that details the process with all the necessary tools to use and model constraints to enforce.
Speed Regulation Example
The Speed Regulation Example shows how to model a system and makes an evaluation for the different criteria:
- Processor resources
- Safety Analysis
The isolette example has its own specific space on the wiki, you can learn more on our dedicated Isolette example page.
An example that combines error and behavior modeling using the AADL error and behavior annexes. Please see the dedicated Robot example page.
The ARP4761 standard defines an example of a Wheel Brake Control System (WBS) with fault and propagations to achieve system safety evaluation and assesment. The full model is detailed in the following page.
An example of an embedded system with three sensors, three processors and two actuators. The model uses the Error-Model Annex and experiments the use of its associated plug-in. In particular, the following features can be used on the following model:
- Fault Hazard Analysis
- Reliability Block Diagram
- Export to PRISM
Two version of the example are available:
- The basic embedded control that is used in several tutorials and presentation and covers the basic use of PRISM
- The advanced version that uses error propagation and export them into PRISM.
Ocarina contains a complete testsuite that includes a lot of models, either for AADLv1 or AADLv2. You can check them on the subversion repository.
PolyORB-HI-C, the AADL runtime used by Ocarina, includes some AADL models for AADLv1 and AADLv2. They can be found in the subversion repository: